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Document Number: 326768-004 Mobile 3rd Generation Intel® Core™ Processor FamilyDatasheet – Volume 1 of 2September 2012

10 Datasheet, Volume 1

Electrical Specifications100 Datasheet, Volume 17.6 Signal GroupsSignals are grouped by buffer type and similar characteristics as listed in Table 7-3

Datasheet, Volume 1 101Electrical Specifications Notes:1. Refer to Chapter 6 for signal description details.2. SA and SB refer to DDR3 Channel A and D

Electrical Specifications102 Datasheet, Volume 17.7 Test Access Port (TAP) ConnectionDue to the voltage levels supported by other components in the Te

Datasheet, Volume 1 103Electrical Specifications 7.9 DC SpecificationsThe processor DC specifications in this section are defined at the processor pin

Electrical Specifications104 Datasheet, Volume 1Notes:1. Unless otherwise noted, all specifications in this table are based on post-silicon estimates

Datasheet, Volume 1 105Electrical Specifications Note:1. Long term reliability cannot be assured in conditions above or below Max / Min functional lim

Electrical Specifications106 Datasheet, Volume 1Note:1. Long term reliability cannot be assured in conditions above or below Max / Min functional limi

Datasheet, Volume 1 107Electrical Specifications 3. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the soc

Electrical Specifications108 Datasheet, Volume 1Notes:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2

Datasheet, Volume 1 109Electrical Specifications Notes:1. Refer to the PCI Express Base Specification for more details.2. Low impedance defined during

Datasheet, Volume 1 11Introduction 1 IntroductionThe Mobile 3rd Generation Intel® Core™ processor family is the next generation of 64-bit, multi-core

Electrical Specifications110 Datasheet, Volume 17.10 Platform Environmental Control Interface (PECI) DC SpecificationsPECI is an Intel proprietary int

Datasheet, Volume 1 111Electrical Specifications 7.10.2 PECI DC CharacteristicsThe PECI interface operates at a nominal voltage set by VCCIO The set o

Electrical Specifications112 Datasheet, Volume 1§ §

Datasheet, Volume 1 113Processor Pin, Signal, and Package Information 8 Processor Pin, Signal, and Package Information8.1 Processor Pin AssignmentsFig

Processor Pin, Signal, and Package Information114 Datasheet, Volume 1Table 8-1. rPGA988B Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 115PEG_RX#[5] H34 PCIe IPEG_RX#[6] H31 PCIe IPEG_RX#[7] G33 PCIe IPEG_RX#[8] G30 PC

Processor Pin, Signal, and Package Information116 Datasheet, Volume 1RSVD AK32RSVD AK2RSVD AJ32RSVD AJ27RSVD AJ26RSVD_NCTF AT34RSVD_NCTF B35RSVD_NCTF

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 117SA_DQ[43] AK9 DDR3 I/OSA_DQ[44] AH8 DDR3 I/OSA_DQ[45] AH9 DDR3 I/OSA_DQ[46] AL9

Processor Pin, Signal, and Package Information118 Datasheet, Volume 1SB_DQ[24] M5 DDR3 I/OSB_DQ[25] N4 DDR3 I/OSB_DQ[26] N2 DDR3 I/OSB_DQ[27] N1 DDR3

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 119VAXG AH23 PWRVAXG AH24 PWRVAXG AJ17 PWRVAXG AJ18 PWRVAXG AJ20 PWRVAXG AJ21 PWRVA

Introduction12 Datasheet, Volume 1Figure 1-1. Mobile Processor PlatformIntel®Flexible Display InterfaceDMI2 x4Discrete Graphics (PEG)Analog CRTGigabit

Processor Pin, Signal, and Package Information120 Datasheet, Volume 1VCC AG28 PWRVCC AG29 PWRVCC AG30 PWRVCC AG31 PWRVCC AG32 PWRVCC AG33 PWRVCC AG34

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 121VCCIO F13 PWRVCCIO F14 PWRVCCIO G13 PWRVCCIO G14 PWRVCCIO H14 PWRVCCIO J13 PWRVC

Processor Pin, Signal, and Package Information122 Datasheet, Volume 1VSS AH4 GNDVSS AH7 GNDVSS AJ1 GNDVSS AJ10 GNDVSS AJ13 GNDVSS AJ16 GNDVSS AJ19 GND

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 123VSS B15 GNDVSS B17 GNDVSS B19 GNDVSS B2 GNDVSS B22 GNDVSS B3 GNDVSS B5 GNDVSS B7

Processor Pin, Signal, and Package Information124 Datasheet, Volume 1VSS N30 GNDVSS N31 GNDVSS N32 GNDVSS N33 GNDVSS N34 GNDVSS N35 GNDVSS P2 GNDVSS P

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 125Figure 8-2. BGA1224 Ballmap (left side)65 64 63 62 61 60 59 58 57 56 55 54 53 52

Processor Pin, Signal, and Package Information126 Datasheet, Volume 1Figure 8-3. BGA1224 Ballmap (right side) 3534333231302928272625242322212019181716

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 127Table 8-2. BGA1224 Processor Ball List by Ball Name Ball Name Ball # Buffer Type

Processor Pin, Signal, and Package Information128 Datasheet, Volume 1eDP_COMPIO AC2 Analog IeDP_HPD# AE8 Asynch CMOS IeDP_ICOMPO AB1 Analog IeDP_TX#[0

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 129PEG_TX#[6] A14 PCIe OPEG_TX#[7] D17 PCIe OPEG_TX#[8] B15 PCIe OPEG_TX#[9] E16 PC

Datasheet, Volume 1 13Introduction 1.1 Processor Feature Details• Four or two execution cores• A 32-KB instruction and 32-KB data first-level cache (L

Processor Pin, Signal, and Package Information130 Datasheet, Volume 1RSVD BA48RSVD BA16RSVD AY45RSVD AY41RSVD AY17RSVD AY15RSVD AY13RSVD AW50RSVD AW46

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 131SA_DQ[13] AR6 DDR3 I/OSA_DQ[14] AW6 DDR3 I/OSA_DQ[15] AT9 DDR3 I/OSA_DQ[16] BA6

Processor Pin, Signal, and Package Information132 Datasheet, Volume 1SA_MA[7] BD21 DDR3 OSA_MA[8] BC22 DDR3 OSA_MA[9] BB21 DDR3 OSA_MA[10] AW38 DDR3 O

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 133SB_DQ[49] BC62 DDR3 I/OSB_DQ[50] AU62 DDR3 I/OSB_DQ[51] AW64 DDR3 I/OSB_DQ[52] B

Processor Pin, Signal, and Package Information134 Datasheet, Volume 1VAXG AE64 PWRVAXG AE62 PWRVAXG AE60 PWRVAXG AD65 PWRVAXG AD63 PWRVAXG AD61 PWRVAX

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 135VCC M46 PWRVCC M42 PWRVCC M40 PWRVCC M36 PWRVCC M34 PWRVCC M29 PWRVCC M27 PWRVCC

Processor Pin, Signal, and Package Information136 Datasheet, Volume 1VCC C28 PWRVCC C26 PWRVCC B45 PWRVCC B43 PWRVCC B41 PWRVCC B37 PWRVCC B35 PWRVCC

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 137VCCIO AH11 PWRVCCIO AF16 PWRVCCIO AF14 PWRVCCIO AE17 PWRVCCIO AE15 PWRVCCIO AE12

Processor Pin, Signal, and Package Information138 Datasheet, Volume 1VDDQ AU30 PWRVDDQ AU26 PWRVDDQ AU24 PWRVDDQ AT46 PWRVDDQ AT42 PWRVDDQ AT40 PWRVDD

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 139VSS BE34 GNDVSS BE30 GNDVSS BE26 GNDVSS BE22 GNDVSS BE18 GNDVSS BE14 GNDVSS BE10

Introduction14 Datasheet, Volume 1• Processor on-die Reference Voltage (VREF) generation for both DDR3 Read (RDVREF) and Write (VREFDQ)• 1Gb, 2Gb, and

Processor Pin, Signal, and Package Information140 Datasheet, Volume 1VSS AU22 GNDVSS AU16 GNDVSS AU14 GNDVSS AT61 GNDVSS AT57 GNDVSS AT50 GNDVSS AT44

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 141VSS AF5 GNDVSS AE57 GNDVSS AD16 GNDVSS AD14 GNDVSS AD7 GNDVSS AD3 GNDVSS AD1 GND

Processor Pin, Signal, and Package Information142 Datasheet, Volume 1VSS L50 GNDVSS L46 GNDVSS L42 GNDVSS L36 GNDVSS L30 GNDVSS L24 GNDVSS L20 GNDVSS

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 143VSS C30 GNDVSS C20 GNDVSS C16 GNDVSS C12 GNDVSS C8 GNDVSS B39 GNDVSS B33 GNDVSS

Processor Pin, Signal, and Package Information144 Datasheet, Volume 1Figure 8-4. BGA1023 Ballmap (left side)61 60 59 58 57 56 55 54 53 52 51 50 49 48

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 145Figure 8-5. BGA1023 Ballmap (right side) 33 32 31 30 29 28 27 26 25 24 23 22 21

Processor Pin, Signal, and Package Information146 Datasheet, Volume 1Table 8-3. BGA1023 Processor Ball List by Ball Name Ball Name Ball # Buffer Type

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 147eDP_COMPIO AF3 Analog IeDP_HPD# AG11 Asynch CMOS IeDP_ICOMPO AD2 Analog IeDP_TX#

Processor Pin, Signal, and Package Information148 Datasheet, Volume 1PEG_TX#[6] K15 PCIe OPEG_TX#[7] F17 PCIe OPEG_TX#[8] F14 PCIe OPEG_TX#[9] A15 PCI

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 149SA_BS[1] BF36 DDR3 OSA_BS[2] BA28 DDR3 OSA_CAS# BE39 DDR3 OSA_CKE[0] AY26 DDR3 O

Datasheet, Volume 1 15Introduction • PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI

Processor Pin, Signal, and Package Information150 Datasheet, Volume 1SA_DQ[63] AK56 DDR3 I/OSA_DQS#[0] AL11 DDR3 I/OSA_DQS#[1] AR8 DDR3 I/OSA_DQS#[2]

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 151SB_DQ[25] BE17 DDR3 I/OSB_DQ[26] BE18 DDR3 I/OSB_DQ[27] BE21 DDR3 I/OSB_DQ[28] B

Processor Pin, Signal, and Package Information152 Datasheet, Volume 1SB_WE# BD45 DDR3 OSM_DRAMPWROK BE45 Asynch CMOS ISM_DRAMRST# AT30 DDR3 OSM_RCOMP[

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 153VCC N30 PWRVCC N26 PWRVCC L40 PWRVCC L36 PWRVCC L33 PWRVCC L28 PWRVCC L25 PWRVCC

Processor Pin, Signal, and Package Information154 Datasheet, Volume 1VCC_SENSE F43 Analog OVCC_VAL_SENSE H43 Analog OVCCDQ AN26 PWRVCCDQ AM28 PWRVCCIO

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 155VCCSA N16 PWRVCCSA L21 PWRVCCSA L17 PWRVCCSA_SENSE U10 Analog OVCCSA_VID[0] D48

Processor Pin, Signal, and Package Information156 Datasheet, Volume 1VSS AY55 GNDVSS AY49 GNDVSS AY45 GNDVSS AY41 GNDVSS AY36 GNDVSS AY30 GNDVSS AY19

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 157VSS AL28 GNDVSS AL25 GNDVSS AL21 GNDVSS AL17 GNDVSS AL13 GNDVSS AL10 GNDVSS AK52

Processor Pin, Signal, and Package Information158 Datasheet, Volume 1VSS W13 GNDVSS W8 GNDVSS V61 GNDVSS V20 GNDVSS U13 GNDVSS U8 GNDVSS T56 GNDVSS T5

Processor Pin, Signal, and Package InformationDatasheet, Volume 1 159VSS F40 GNDVSS F35 GNDVSS F29 GNDVSS F19 GNDVSS F15 GNDVSS F13 GNDVSS E40 GNDVSS

Introduction16 Datasheet, Volume 1• 64-bit downstream address format; however, the processor never generates an address above 64 GB (Bits 63:36 will a

Processor Pin, Signal, and Package Information160 Datasheet, Volume 18.2 Package Mechanical InformationFigure 8-6. Processor rPGA988B 2C/GT1 (G24406)

Datasheet, Volume 1 161Processor Pin, Signal, and Package Information Figure 8-7. Processor rPGA988B 2C/GT1 (G24406) Mechanical Package (Sheet 2 of 2)

Processor Pin, Signal, and Package Information162 Datasheet, Volume 1Figure 8-8. Processor rPGA988B 2C/GT2 (G23867) Mechanical Package (Sheet 1 of 2)

Datasheet, Volume 1 163Processor Pin, Signal, and Package Information Figure 8-9. Processor rPGA988B 2C/GT2 (G23867) Mechanical Package (Sheet 2 of 2)

Processor Pin, Signal, and Package Information164 Datasheet, Volume 1Figure 8-10. Processor rPGA988B 4C/GT2 (E95127) Mechanical Package (Sheet 1 of 2)

Datasheet, Volume 1 165Processor Pin, Signal, and Package Information Figure 8-11. Processor rPGA988B 4C/GT2 (E95127) Mechanical Package (Sheet 2 of 2

Processor Pin, Signal, and Package Information166 Datasheet, Volume 1Figure 8-12. Processor BGA1023 2C/GT1 (G24405) Mechanical Package

Datasheet, Volume 1 167Processor Pin, Signal, and Package Information Figure 8-13. Processor BGA1023 2C/GT2 (G23866) Mechanical Package

Processor Pin, Signal, and Package Information168 Datasheet, Volume 1§ §Figure 8-14. Processor BGA1224 4C/GT2 (G26204) Mechanical Package

Datasheet, Volume 1 169DDR Data Swizzling 9 DDR Data SwizzlingTo achieve better memory performance and timing, Intel Design performed DDR Data pin swi

Datasheet, Volume 1 17Introduction 1.2.6 Embedded DisplayPort* (eDP*)• Stand alone dedicated port (unlike two generations ago that shared pins with PC

DDR Data Swizzling170 Datasheet, Volume 1Table 9-1. DDR Data Swizzling Table – Channel APin NamePin Number rPGAPin Number BGA1023Pin Number BGA1224MC

DDR Data SwizzlingDatasheet, Volume 1 171§ §Table 9-2. DDR Data Swizzling Table for Package – Channel BPin NamePin NumberrPGABall Number BGA1023Ball

DDR Data Swizzling172 Datasheet, Volume 1

Introduction18 Datasheet, Volume 11.3.6 Processor Graphics Controller (GT)•Intel® Rapid Memory Power Management (Intel® RMPM) – CxSR•Intel® Graphics P

Datasheet, Volume 1 19Introduction 1.5 PackageThe processor is available on two packages:• A 37.5 x 37.5 mm rPGA package (rPGA988B)• A 31 x 24 mm BGA

2 Datasheet, Volume 1INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERW

Introduction20 Datasheet, Volume 11.7 TerminologyTable 1-2. Terminology (Sheet 1 of 3)Term DescriptionACPI Advanced Configuration and Power Interface

Datasheet, Volume 1 21Introduction Intel® VT-dIntel® Virtualization Technology (Intel® VT) for Directed I/O. Intel VT-d is a hardware assist, under s

Introduction22 Datasheet, Volume 1SVID Serial Voltage IDentification interfaceTAC Thermal Averaging ConstantTAP Test Access PointTCC Thermal Control C

Datasheet, Volume 1 23Introduction 1.8 Related DocumentsNote: Contact your Intel representative for the latest revision of this item.§ §Table 1-3. Rel

Introduction24 Datasheet, Volume 1

Datasheet, Volume 1 25Interfaces 2 InterfacesThis chapter describes the interfaces supported by the processor.2.1 System Memory Interface2.1.1 System

Interfaces26 Datasheet, Volume 1Note:1. System memory configurations are based on availability and are subject to change.2.1.2 System Memory Timing Su

Datasheet, Volume 1 27Interfaces Note:1. System memory timing support is based on availability and is subject to change.Note:1. System memory timing s

Interfaces28 Datasheet, Volume 1Note: Channels A and B can be mapped for physical channel 0 and 1 respectively or vice versa; however, channel A size

Datasheet, Volume 1 29Interfaces 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)The following sections describe the Just-in-Ti

Datasheet, Volume 1 3 Contents1Introduction...

Interfaces30 Datasheet, Volume 12.1.8 DDR3 Reference Voltage GenerationThe processor memory controller has the capability of generating the DDR3 Refer

Datasheet, Volume 1 31Interfaces PCI Express uses packets to communicate information between components. Packets are formed in the Transaction and Dat

Interfaces32 Datasheet, Volume 12.2.2 PCI Express* Configuration MechanismThe PCI Express (external graphics) link is mapped through a PCI-to-PCI brid

Datasheet, Volume 1 33Interfaces 2.2.3 PCI Express* GraphicsThe external graphics attach (PEG) on the processor is a single, 16-lane (x16) port. The P

Interfaces34 Datasheet, Volume 12.3 Direct Media Interface (DMI)Direct Media Interface (DMI) connects the processor and the PCH. Next generation DMI 2

Datasheet, Volume 1 35Interfaces 2.4 Processor Graphics Controller (GT)New Graphics Engine Architecture includes 3D compute elements, Multi-format har

Interfaces36 Datasheet, Volume 12.4.1.2 3D Pipeline2.4.1.2.1 Vertex Fetch (VF) StageThe VF stage executes 3DPRIMITIVE commands. Some enhancements have

Datasheet, Volume 1 37Interfaces 2.4.1.4 2D EngineThe Display Engine fetches the raw data from the memory, puts the data into a stream, converts the d

Interfaces38 Datasheet, Volume 12.4.2 Processor Graphics DisplayThe Processor Graphics controller display pipe can be broken down into three component

Datasheet, Volume 1 39Interfaces 2.4.2.2 Display PipesThe display pipe blends and synchronizes pixel data received from one or more display planes and

4 Datasheet, Volume 12.3.3 DMI Link Down...342.4 Processor Graphic

Interfaces40 Datasheet, Volume 12.4.4 Multi Graphics Controllers Multi-Monitor Support The processor supports simultaneous use of the Processor Graphi

Datasheet, Volume 1 41Technologies 3 TechnologiesThis chapter provides a high-level description of Intel technologies implemented in the processor.The

Technologies42 Datasheet, Volume 13.1.2 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Featu

Datasheet, Volume 1 43Technologies 3.1.4 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) FeaturesThe processor supports th

Technologies44 Datasheet, Volume 13.2 Intel® Trusted Execution Technology (Intel® TXT)Intel Trusted Execution Technology (Intel TXT) defines platform-

Datasheet, Volume 1 45Technologies 3.4 Intel® Turbo Boost TechnologyIntel Turbo Boost Technology will increase the ratio of application power to TDP.

Technologies46 Datasheet, Volume 13.4.2 Intel® Turbo Boost Technology Graphics FrequencyThe graphics render frequency is selected dynamically based on

Datasheet, Volume 1 47Technologies 3.6 Security and Cryptography Technologies3.6.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI

Technologies48 Datasheet, Volume 13.7 Intel® 64 Architecture x2APICThe Intel x2APIC architecture extends the xAPIC architecture that provides key mech

Datasheet, Volume 1 49Technologies The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the “x2APIC” mode.

Datasheet, Volume 1 5 4.2.1 Enhanced Intel® SpeedStep® Technology...544.2.2 Low-Power Idle States ...

Technologies50 Datasheet, Volume 1

Datasheet, Volume 1 51Power Management 4 Power ManagementThis chapter provides information on the following power management topics:• Advanced Configu

Power Management52 Datasheet, Volume 14.1 Advanced Configuration and Power Interface (ACPI) States SupportedThe ACPI states supported by the processor

Datasheet, Volume 1 53Power Management 4.1.4 PCI Express* Link States4.1.5 Direct Media Interface (DMI) States4.1.6 Processor Graphics Controller Stat

Power Management54 Datasheet, Volume 14.2 Processor Core Power ManagementWhile executing code, Enhanced Intel SpeedStep Technology optimizes the proce

Datasheet, Volume 1 55Power Management 4.2.2 Low-Power Idle StatesWhen the processor is idle, low-power idle states (C-states) are used to save power.

Power Management56 Datasheet, Volume 1Note: If enabled, the core C-state will be C1E if all cores have resolved a core C1 state or higher.4.2.3 Reques

Datasheet, Volume 1 57Power Management 4.2.4 Core C-statesThe following are general rules for all core C-states, unless specified otherwise:• A core C

Power Management58 Datasheet, Volume 14.2.4.5 Core C7 StateNote: The terms “Core C6 state” and “Core C7 state” defines the same individual core power

Datasheet, Volume 1 59Power Management The processor exits a package C-state when a break event is detected. Depending on the type of break event, the

6 Datasheet, Volume 15.6.2 Digital Thermal Sensor ...805.6.2.1 Digital Therma

Power Management60 Datasheet, Volume 14.2.5.1 Package C0Package C0 is the normal operating state for the processor. The processor remains in the norma

Datasheet, Volume 1 61Power Management 4.2.5.5 Package C7 StateThe processor enters the package C7 low power state when all cores are in the C7 state

Power Management62 Datasheet, Volume 14.3.2 DRAM Power Management and InitializationThe processor implements extensive support for power management on

Datasheet, Volume 1 63Power Management It is important to understand that since the power down decision is per rank, the MC can find a lot of opportun

Power Management64 Datasheet, Volume 1The target behavior is to enter self-refresh for the package C3, C6, and C7 states as long as there are no memor

Datasheet, Volume 1 65Power Management There is no change to the signals driven by the processor to the DIMMs during DDR IO EPG mode.During EPG mode,

Power Management66 Datasheet, Volume 14.6.3 Graphics Render C-StateRender C-State (RC6) is a technique designed to optimize the average power to the g

Datasheet, Volume 1 67Power Management 4.6.6 Display Power Savings Technology 6.0 (DPST)This is a mobile only supported power management feature.The I

Power Management68 Datasheet, Volume 14.7 Graphics Thermal Power ManagementSee Section 4.6 for all graphics thermal power management-related features.

Datasheet, Volume 1 69Thermal Management 5 Thermal ManagementThe thermal solution provides both the component-level and the system-level thermal manag

Datasheet, Volume 1 7 Figures1-1 Mobile Processor Platform...121-

Thermal Management70 Datasheet, Volume 15.2 Intel® Turbo Boost Technology Power MonitoringWhen operating in the Turbo mode, the processor will monitor

Datasheet, Volume 1 71Thermal Management Table 5-1. Intel® Turbo Boost Technology Package Power Control SettingsMSR:Address:MSR_TURBO_POWER_LIMIT610hC

Thermal Management72 Datasheet, Volume 15.3.2 Power Plane ControlThe processor core and graphics core power plane controls allow for customization to

Datasheet, Volume 1 73Thermal Management The cTDP consists of three modes as shown in Table 5-2.In each mode, the Intel Turbo Boost Technology power a

Thermal Management74 Datasheet, Volume 15.5 Thermal and Power SpecificationsThe following notes apply to the tables in this section. Note Definition1T

Datasheet, Volume 1 75Thermal Management Table 5-3. Thermal Design Power (TDP) SpecificationsSegment StateProcessor Core FrequencyProcessor Graphics C

Thermal Management76 Datasheet, Volume 1Table 5-5. Package Turbo Parameters Segment Symbol Package Turbo Parameter MinHW DefaultMax Units NotesExtreme

Datasheet, Volume 1 77Thermal Management 5.6 Thermal Management FeaturesThermal management features for the entire processor complex (including the pr

Thermal Management78 Datasheet, Volume 1The temperature at which the Adaptive Thermal Monitor activates the thermal control circuit is factory calibra

Datasheet, Volume 1 79Thermal Management Once a target frequency/bus ratio is resolved, the processor core will transition to the new target automatic

8 Datasheet, Volume 14-11 Coordination of Core Power States at the Package Level ...594-12 Targeted Memory

Thermal Management80 Datasheet, Volume 15.6.1.3 Clock ModulationIf the frequency/voltage changes are unable to end an Adaptive Thermal Monitor event,

Datasheet, Volume 1 81Thermal Management The DTS-relative temperature readout directly impacts the Adaptive Thermal Monitor trigger point. When a pack

Thermal Management82 Datasheet, Volume 1The TCC will remain active until the system de-asserts PROCHOT#. The processor can be configured to generate a

Datasheet, Volume 1 83Thermal Management 5.6.3.5 THERMTRIP# SignalRegardless of enabling the automatic or on-demand modes, in the event of a catastrop

Thermal Management84 Datasheet, Volume 15.6.5 Memory Thermal ManagementThe integrated memory controller (IMC) provides thermal protection for system m

Datasheet, Volume 1 85Signal Description 6 Signal DescriptionThis chapter describes the processor signals. They are arranged in functional groups acco

Signal Description86 Datasheet, Volume 16.1 System Memory Interface SignalsTable 6-2. Memory Channel A Signals Signal Name Description Direction/Buffe

Datasheet, Volume 1 87Signal Description Table 6-3. Memory Channel B Signals Signal Name Description Direction/Buffer TypeSB_BS[2:0]Bank Select: These

Signal Description88 Datasheet, Volume 16.2 Memory Reference and Compensation Signals6.3 Reset and Miscellaneous SignalsTable 6-4. Memory Reference an

Datasheet, Volume 1 89Signal Description 6.4 PCI Express*-based Interface Signals6.5 Embedded DisplayPort* (eDP*) Signals6.6 Intel® Flexible Display (

Datasheet, Volume 1 9 Revision History§ §Revision NumberDescription Revision Date001 • Initial release April 2012002• Added Mobile 3rd Generation Inte

Signal Description90 Datasheet, Volume 16.7 Direct Media Interface (DMI) Signals6.8 Phase Lock Loop (PLL) Signals6.9 Test Access Points (TAP) SignalsF

Datasheet, Volume 1 91Signal Description 6.10 Error and Thermal Protection SignalsPRDY#PRDY# is a processor output used by debug tools to determine pr

Signal Description92 Datasheet, Volume 16.11 Power Sequencing SignalsTable 6-13. Power Sequencing Signals Signal Name Description Direction/Buffer Typ

Datasheet, Volume 1 93Signal Description 6.12 Processor Power SignalsNote:1. The VCCSA_VID can toggle at most once in 500 uS; The slew rate of VCCSA_V

Signal Description94 Datasheet, Volume 16.14 Ground and Non-Critical to Function (NCTF) Signals6.15 Processor Internal Pull-Up / Pull-Down Resistors§

Datasheet, Volume 1 95Electrical Specifications 7 Electrical Specifications7.1 Power and Ground PinsThe processor has VCC, VCCIO, VDDQ, VCCPLL, VCCSA,

Electrical Specifications96 Datasheet, Volume 17.3 Voltage Identification (VID)The processor uses three signals for the serial voltage identification

Datasheet, Volume 1 97Electrical Specifications 0 0 0 1 1 0 0 0 1 8 0.36500 1 0 0 1 1 0 0 0 9 8 1.005000 0 0 1 1 0 0 1 1 9 0.37000 1 0 0 1 1 0 0 1 9 9

Electrical Specifications98 Datasheet, Volume 10 1 0 1 0 0 0 1 5 1 0.65000 1 1 0 1 0 0 0 1 D 1 1.290000 1 0 1 0 0 1 0 5 2 0.65500 1 1 0 1 0 0 1 0 D 2

Datasheet, Volume 1 99Electrical Specifications 7.4 System Agent (SA) Vcc VIDThe VCCSA is configured by the processor output pins VCCSA_VID[1:0].VCCSA