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Datasheet, Volume 1 169
DDR Data Swizzling
9 DDR Data Swizzling
To achieve better memory performance and timing, Intel Design performed DDR Data
pin swizzling that allows a better use of the product across different platforms.
Swizzling has no effect on functional operation and is invisible to the operating
system/software.
However, during debug, swizzling needs to be taken into consideration. Therefore, this
swizzling information is presented. When placing a DIMM logic analyzer, the design
engineer must pay attention to the swizzling table to be able to debug memory
efficiently.
- Mobile 3rd Generation Intel 1
- Processor Family 1
- 2 Datasheet, Volume 1 2
- Contents 3
- 4 Datasheet, Volume 1 4
- Datasheet, Volume 1 5 5
- 6 Datasheet, Volume 1 6
- Datasheet, Volume 1 7 7
- 8 Datasheet, Volume 1 8
- Revision History 9
- 10 Datasheet, Volume 1 10
- 1 Introduction 11
- Processor 12
- 1.1 Processor Feature Details 13
- 1.2 Interfaces 13
- 1.2.2 PCI Express* 14
- Datasheet, Volume 1 15 15
- Introduction 15
- 1.2.5 Processor Graphics 16
- 1.3 Power Management Support 17
- 1.5 Package 19
- 1.6 Processor Compatibility 19
- 1.7 Terminology 20
- 1.8 Related Documents 23
- 24 Datasheet, Volume 1 24
- 2 Interfaces 25
- 2.1.3.1 Single-Channel Mode 27
- Flex Memory Technology Mode 27
- Interfaces 28
- 28 Datasheet, Volume 1 28
- 2.1.5.2 Command Overlap 29
- 2.2 PCI Express* Interface 30
- 2.2.1.1 Transaction Layer 31
- 2.2.1.2 Data Link Layer 31
- 2.2.1.3 Physical Layer 31
- 32 Datasheet, Volume 1 32
- 2.2.3 PCI Express* Graphics 33
- 2.3.1 DMI Error Flow 34
- 2.3.3 DMI Link Down 34
- Datasheet, Volume 1 35 35
- 2.4.1.2 3D Pipeline 36
- 2.4.1.3 Video Engine 36
- 2.4.1.4 2D Engine 37
- 2.4.2.1 Display Planes 38
- 2.4.2.2 Display Pipes 39
- 2.4.2.3 Display Ports 39
- 2.6 Interface Clocking 40
- 3 Technologies 41
- Technologies 42
- 42 Datasheet, Volume 1 42
- Datasheet, Volume 1 43 43
- 44 Datasheet, Volume 1 44
- 3.4 Intel 45
- Turbo Boost Technology 45
- 3.5 Intel 46
- Datasheet, Volume 1 47 47
- 3.7 Intel 48
- 64 Architecture x2APIC 48
- Datasheet, Volume 1 49 49
- 50 Datasheet, Volume 1 50
- 4 Power Management 51
- (ACPI) States Supported 52
- 4.2.1 Enhanced Intel 54
- SpeedStep 54
- Technology 54
- 4.2.2 Low-Power Idle States 55
- 4.2.4.1 Core C0 State 57
- 4.2.4.2 Core C1 / C1E State 57
- 4.2.4.3 Core C3 State 57
- 4.2.4.4 Core C6 State 57
- 4.2.4.5 Core C7 State 58
- 4.2.4.6 C-State Auto-Demotion 58
- 4.2.5.1 Package C0 60
- 4.2.5.2 Package C1/C1E 60
- 4.2.5.3 Package C3 State 60
- 4.2.5.4 Package C6 State 60
- 4.2.5.5 Package C7 State 61
- Management 61
- Power Management 62
- 62 Datasheet, Volume 1 62
- Datasheet, Volume 1 63 63
- 4.5 DMI Power Management 65
- 4.6 Graphics Power Management 65
- 66 Datasheet, Volume 1 66
- Datasheet, Volume 1 67 67
- 68 Datasheet, Volume 1 68
- 5 Thermal Management 69
- 5.2 Intel 70
- 5.3 Intel 70
- System Thermal Response Time 71
- Low Power Mode (LPM) 72
- Thermal Management 73
- Mode Description 73
- Note Definition 74
- Max Units Notes 76
- Segment Symbol 77
- Idle Parameter Min Typ Max 77
- Units Notes 77
- 5.6.1.1 TCC Activation Offset 78
- 5.6.1.3 Clock Modulation 80
- 82 Datasheet, Volume 1 82
- 5.6.3.5 THERMTRIP# Signal 83
- 84 Datasheet, Volume 1 84
- 6 Signal Description 85
- Table 6-8. Intel 89
- Flexible Display (Intel 89
- 6.11 Power Sequencing Signals 92
- 6.12 Processor Power Signals 93
- 6.13 Sense Signals 93
- 7 Electrical Specifications 95
- 7.4 System Agent (SA) Vcc VID 99
- 7.6 Signal Groups 100
- (Prior to Board Attach) 102
- 7.9 DC Specifications 103
- Table 7-5. Processor Core (V 104
- Electrical Specifications 105
- Table 7-9. Processor PLL (V 106
- DC Specifications 110
- 112 Datasheet, Volume 1 112
- 8 Processor Pin, Signal, and 113
- Datasheet, Volume 1 125 125
- 126 Datasheet, Volume 1 126
- 144 Datasheet, Volume 1 144
- Datasheet, Volume 1 145 145
- 160 Datasheet, Volume 1 160
- Datasheet, Volume 1 161 161
- 162 Datasheet, Volume 1 162
- Datasheet, Volume 1 163 163
- 164 Datasheet, Volume 1 164
- Datasheet, Volume 1 165 165
- 166 Datasheet, Volume 1 166
- Datasheet, Volume 1 167 167
- 168 Datasheet, Volume 1 168
- 9 DDR Data Swizzling 169
- Table – Channel A 170
- DDR Data Swizzling 172
- 172 Datasheet, Volume 1 172
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