HP B160L Manual de usuario Pagina 24

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PA-RISC Processors PA-7200 (PCX-T’) (Thunderbird’)
SMP-capable
FPU, MMU, cache controller integrated on die, memory and I/O controller separate and off-chip
Five-stage pipeline
2KB on-chip “assist” L1 cache, fully associative, holds 64 32-Byte cache lines
Off-chip L1 caches up to 1MB I and 2MB D realized in asynchronous SRAMs with one cycle
latency
(The 2KB on-chip assist cache is not really considered a true cache, thus the off-chip cache is the
system’s L1 cache.)
Caches are 64-bit per access, direct mapped, parity protected and cycled at CPU speed
Caches are virtually indexed and physically tagged to minimize latency
120-entry fully associative TLB
16-entry BTLB
Hardware TLB miss support
Six predecode bits
Support for uncached memory pages
Bi-endian support
Runway system interface, 64-bit wide, 120MHz, 960MB/s peak bandwidth, CPU-to-bus fre-
quency ratios of 1.0, 0.75 and .67 processor speed possible
Glueless interface to the Runway system bus for up to four-way SMP (four CPUs on same Runway
processor bus)
Can have up to six bus-transactions in progress at once
CPU interfaces to U2 I/O adapters and MMC/SMC memory controllers on the Runway bus
Up to 140MHz frequency with 4.4V core and 3.3V I/O voltage
14.0×15.0 mm
2
die, 1,300,000 FETs, 0.55µ(micron), 3-layer metal CMOS (CMOS14A process)
packaged in a 540-pin ceramic PGA package
Power dissipation of 29W at 140MHz
References
1. Design of the HP PA 7200 CPU
16
(.pdf) Kenneth K. Chan et al (February 1996: Hewlett-Packard
Journal)
2. A Different Kind of RISC
17
Dick Pountain (August 1994: BYTE Journal)
3. Interview with David Fotland, September/October 2008
16
http://ftp.parisc-linux.org/docs/whitepapers/pa7200_design.pdf
17
http://www.byte.com/art/9408/sec11/art3.htm
17
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